Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

verilog syntax problem

Having been using VHDL for a long time I am struggling with a bit of verilog that my books alone cannot help me translate parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

1) Almost. GATE_BOARD_DQS_DELAY is assigned to 0 or BOARD_DQS_DELAY depending on RTL_DELAYS.

2) It means that the expression that follows is the delay of the wire being declared. It probably won't synthesize in Quartus.

3) You could. Looks like just a style choice on the part of the author.