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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog question- referencing modules?

I've got a system written in Verilog that includes several instances of an arithmetic module block scattered throughout the system hierarchy. We'd like to consolidate these arithmetic module instances into a single instance that multiplexes operations -- thereby reducing the number of logic elements devoted to the arithmetic operation at the expense of more wiring and a delay penalty before getting a result.

In my mind, we'll need to create the multiplexed arithmetic module at the top-level, and then route the I/O from all the blocks that currently rely on separate instances of the module up to this top-level instance. The sticking point is that some of the modules that currently instantiate the arithmetic module are buried pretty deep, so I'd potentially have to update the I/O ports on quite a few blocks to bring the I/O back to the top-level for processing. Ugh.

Being a newbie at Verilog, I'm wondering if there is a simpler method of achieving this. Is there a way to create a single instance of a module and then reference arbitrary ports for that instance by other modules... especially ones that may be 'buried' deep in the design? Or, am I going to be stuck doing it the hard way?

Any and all help will be greatly appreciated!

Thanks,

--tim

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It is possible in verilog to hierarchically reference signals in the design, but I've only used this in test benches, not synthesized code.

    I'm not sure those constructs are supported by Quartus synthesis.

    Here's a good quick reference for Verilog (2001).

    http://www.sutherland-hdl.com/online_verilog_ref_guide/verilog_2001_ref_guide.pdf

    The other question is "Do you want to:" use this method if it's possible.. you will loose a lot of your readability of the code if you all of a sudden yank it out of the hierarchy with no ports, and connect the signals at some other level through hierarchical references...

    My suggestion is you bite the nail and add the ports. Or if the arithmetic function really requires re-use, it probably is better to start from scratch with re-use in mind from the beginning. You will probably have much better data flow and it will be easier for you to understand how it's working..

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Verilog has the concept of hierarchical names that could be helpful for your intentions. But it's unsupported by Quartus in the general form (across modules). So there's no other option than wiring the arithmetic ports through all hierarchies, e.g. using a kind of bus.

    Generally, I think a shared arithmetic unit may be reasonable in special cases, e.g. for extensive float arithmetic. But serializing arithmetic operations across module boundaries questions basic FPGA design concepts. I wonder, if you shouldn't move to a soft processor that carries out all related arithmetic operations. It will serialize operations by design and won't need special measures to schedule it.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for the feedback! It looks like I'll have to do things the "hard" way.

    I had thought about using a softcore processor, but we are strapped for resources which is why we are trying to go with the shared arithmetic module route.

    --tim