Verilog question- referencing modules?

Verilog has the concept of hierarchical names that could be helpful for your intentions. But it's unsupported by Quartus in the general form (across modules). So there's no other option than wiring the arithmetic ports through all hierarchies, e.g. using a kind of bus.

Generally, I think a shared arithmetic unit may be reasonable in special cases, e.g. for extensive float arithmetic. But serializing arithmetic operations across module boundaries questions basic FPGA design concepts. I wonder, if you shouldn't move to a soft processor that carries out all related arithmetic operations. It will serialize operations by design and won't need special measures to schedule it.