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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog question- referencing modules?

I've got a system written in Verilog that includes several instances of an arithmetic module block scattered throughout the system hierarchy. We'd like to consolidate these arithmetic module instance...
Altera_Forum's avatar
Altera_Forum
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15 years ago

It is possible in verilog to hierarchically reference signals in the design, but I've only used this in test benches, not synthesized code.

I'm not sure those constructs are supported by Quartus synthesis.

Here's a good quick reference for Verilog (2001).

http://www.sutherland-hdl.com/online_verilog_ref_guide/verilog_2001_ref_guide.pdf

The other question is "Do you want to:" use this method if it's possible.. you will loose a lot of your readability of the code if you all of a sudden yank it out of the hierarchy with no ports, and connect the signals at some other level through hierarchical references...

My suggestion is you bite the nail and add the ports. Or if the arithmetic function really requires re-use, it probably is better to start from scratch with re-use in mind from the beginning. You will probably have much better data flow and it will be easier for you to understand how it's working..

Pete