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Honored Contributor
Honored ContributorVerilog process not implemented correctly in Quartus
Hi, It seems as though the following synchronous process in Verilog is sometimes not implemented correctly by Quartus. Why? always @(posedge clk, negedge rst_n) if (!rst_n) begin ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, how the signals !srst_n and sof generated ? Outside the FPGA ? Kind regards GPK --- Quote End --- These are synchronous register outputs (synchronous to clk)
