Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Verilog process not implemented correctly in Quartus

Hi, It seems as though the following synchronous process in Verilog is sometimes not implemented correctly by Quartus. Why? always @(posedge clk, negedge rst_n) if (!rst_n) begin ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What Quartus Version are you using ?

if 1 compilation is working and 1 not, what about the others ?

one thing that i am not shure is, shouldn't you write

always @(posedge clk or negedge rst_n)

Did you specify the initial values for hdr_frame_length_s ?

like

reg [15:0] hdr_frame_length_s = 16'd1;

or during

initial

begin

hdr_frame_length_s = 16'd1;

end // of initialiser block

Do you get any warnings during compilation ?

Have a look at this Doc Recomended HDL coding guidelines.

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=4&wt.oss_r=1&wt.oss=hdl design guide (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=4&wt.oss_r=1&wt.oss=hdl design guide)