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Altera_Forum
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16 years ago

Verilog process not implemented correctly in Quartus

Hi, It seems as though the following synchronous process in Verilog is sometimes not implemented correctly by Quartus. Why? always @(posedge clk, negedge rst_n) if (!rst_n) begin ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

It could be the priority logic(if else) and the fact that the sequential last statement overwrites that is causing the problem...