Strictly speaking, if you don't want to use a port on a module, just don't connect it to anything. The synthesis tool is smart enough to remove any logic driving the ports.
Examples:
uart_rx rx1 (
.reset(uart_rst),
.rxclk (baud_clk ),
.rx_read (rs ),
.rx_data (data ),
.rx_in (rx ),
.rx_empty ( ),
.rx_busy ( )
);
or
uart_rx rx1 (
.reset(uart_rst),
.rxclk (baud_clk ),
.rx_read (rs ),
.rx_data (data ),
.rx_in (rx )
);
Alternatively, you can use a macro to get rid of it:
uart_rx rx1 (
.reset(uart_rst),
.rxclk (baud_clk ),
.rx_read (rs ),
.rx_data (data ),
.rx_in (rx )
`ifndef USE_WORTHLESS_PORTS
,
.rx_empty ( ),
.rx_busy ( )
`endif
);
And you can use synthesis directives if you don't want it in there for synthesis but do for simulation:
uart_rx rx1 (
.reset(uart_rst),
.rxclk (baud_clk ),
.rx_read (rs ),
.rx_data (data ),
.rx_in (rx )
// synthesis translate_off
,
.rx_empty ( ),
.rx_busy ( )
// synthesis translate_on
);
Jake