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Altera_Forum
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11 years ago

VERILOG LCELL Simulation

I have implemented a ring oscillator using LCELLs. I am able to simulate it using ModelSim-Altera with the following VHDL statement: ring: for k in 0 to NUM_LUTS-1 generate begin ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

After a few hours of searching, reading and experimenting I finally found out how to simulate it. It's not the way it should be but it works! Verilog is more troublesome to simulate than VHDL. Oh well, the way it is.

Thanks anyway.