Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVerilog Language to desribe top entity
I used a DE2_NIOS project in the Altera CD , and modify(delete some unnecessary modules , and add some pio modules ) it properly to be used as a uclinux project.
Modification is ONLY done in the SOPCBuilder. So I use the default old DE2_NIOS.sof , and the uclinux works on the board. It's quite strange. However, when I compile it in the QuartusII ( only delete some pins in the .v top entity file ) and complete the compilation. and program the newly sof file into the board, uclinux doesn't work. I mean, how to modify the .v top entity file, to become a qualified .v file as the top entity of the project of uclinux.3 Replies
Altera_Forum--- Quote Start --- ¿did you keep the timer module?. ¿doe's a simple Nios II IDE project run on your system? --- Quote End --- Maybe I should re-modify the project in QuartusII, reassign the pins of the project. And the sof file may have its effect , uclinux system can run with it.- Altera_Forum--- Quote Start --- ¿did you keep the timer module?. ¿doe's a simple Nios II IDE project run on your system? --- Quote End --- Actually, I use the example of Altera CD to build a two cpu project. Including the timer module, and set another internal timer for cpu1.
- Altera_Forum
¿did you keep the timer module?.
¿doe's a simple Nios II IDE project run on your system?
