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Altera_Forum
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16 years ago

Verilog Generic Input ports

Hi All, I have an input port to a module which is 5 bits say Inp_A[4:0]. Now the number of such inputs depends on a generic parameter say Gen_Nm. How can i declare such an input ports in m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Schmitt,

The example given

input [4:0] Inp_A [Gen_Num-1:0]; // should give Gen_Num x 5 bit input

is not working.

The compiler is throwing error saying that, this is a System Verilog construct.

Verilog does not support Memory type port declaration.

What is your thoughts on this .

regards,

freak