Verilog Generic Input ports

your last example is the correct one.

check that parameter is declared within the same file like :

module dummy_mod( Inp_A );

parameter Gen_Num = 3

input [4:0] Inp_A [Gen_Num-1:0]; // should give Gen_Num x 5 bit input

endmodule

but i have seen that quartus sometimes seems to have problems with parameters

if i use them then i do the following

parameter ReloadValue = 47;

wire [5:0] wReloadValue;

assign wReloadValue = ReloadValue;

somewhere this can be used as

rTestReg <= rMyValue + wReloadValue ;

assigning a wire with the parameter works, using the parameter directly doesn't

no idea why