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Altera_Forum's avatar
Altera_Forum
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16 years ago

Verilog Generate

Hi All, Does verilog allows to use generate statements inside another generate statement. I have a requirement as shon below, generate if (A >1) // A is a top level generic gen...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanx Jake. This was a very useful tip.

I have one more query.

Can i have some king of code as shown below. i.e.multiple for loops inside same generate.

Code:

generate if (A >1)

for (i=0; i< 2; i=i+1)

begin : ZEROTOTWO

assign c = a & b;

end

for (i=2; i< 10; i=i+1)

begin : twototen

assign c = a & b;

end

endgenerate

Please give your thought.

regards,

freak