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Altera_Forum
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17 years ago

Verilog Generate

Hi All, Does verilog allows to use generate statements inside another generate statement. I have a requirement as shon below, generate if (A >1) // A is a top level generic gen...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

But, we can use for loop only inside a always block. This is a problem.

Please share your thoughts.

regards,

freak