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Altera_Forum
Honored Contributor
Honored ContributorVerilog Generate
Hi All,
Does verilog allows to use generate statements inside another generate statement. I have a requirement as shon below, generate if (A >1) // A is a top level generic generate for (i=0; i<10; i=i+1) begin : START logic..... end endgenerate endgenerate The above gives errors while compiling. Any other option to use generate inside another generate. regards, freak5 Replies
Altera_ForumThanx Jake. This was a very useful tip.
I have one more query. Can i have some king of code as shown below. i.e.multiple for loops inside same generate. Code: generate if (A >1) for (i=0; i< 2; i=i+1) begin : ZEROTOTWO assign c = a & b;end
for (i=2; i< 10; i=i+1)
begin : twototen
assign c = a & b; end endgenerate Please give your thought. regards, freak
- Altera_Forum
You could post the code you're trying to make work.
Jake - Altera_Forum
You cannot do a generate inside an always block. You can do an always block inside a generate.
Jake - Altera_Forum
But, we can use for loop only inside a always block. This is a problem.
Please share your thoughts. regards, freak - Altera_Forum
genvar i; generate if (A >1) begin// A is a top level generic for (i=0; i<10; i=i+1) begin : START logic..... end end endgenerate
