Verilog Generate Inquiry

Hello,

I have a question about the usage of generate statements in verilog (not SystemVerilog). I am using Quartus II 9.1 sp2 (subscription ed.) and the Cyclone II (DE2 Board).

For my current application it would be convenient to initialize and increment multiple genvars in one for loop, for example:

 
  genvar i,j;
  generate
    for (i=0, j=0; i < 16; i = i+4, j=j+1)    <--- This
    begin: label
       ....
  endgenerate

The error is 10170, expecting ".", or "(". Similarly this causes an error:

 
  genvar i,j;
  generate
    i = 0;       <--- This
       ....
  endgenerate

Is there any way to assign values in this way or initialize/increment multiple genvars? I know that in an always block, it is possible to do this using integers (but using an integer in the generate block above also generates the same error).

Finally, depending on the state of my state machine I would like to instantiate different modules, however state is a reg. Is there any way to do something like this: (I receive the error that state is not a constant value):

 
  genvar i,j;
  generate
    if (state == 3)       <--- This
       ....
  endgenerate

(These are just examples; specifially I am designing an FFT and need to instantiate many LPM_MULT modules using values stored in arrays of registers. The above examples are sufficient illustrate my questions, but I have also included the portion of my circuit below which includes all the errors mentioned above).

I would greatly appreciate any feedback or suggestions

Thank you

 
  genvar gm, gi, gtemp_count, sin_index; // gm and gi are for loop indices
  generate
    if (state == 2)
    begin  
      gtemp_count = 0;
      for (sin_index = 0, gm=0; gm<2; gm=gm+1, sin_index = sin_index + 2) // Unfortunately sin_index needs to change in this for loop as well
      begin : outer
        for (gi=gm; gi<64; gi=gi+2, gtemp_count = gtemp_count + 1) //  same with gtemp_count, it would be convenient to change both
        begin : inner
          mult M1 (clock, sin_lookup, Imag, temp1);
          mult M2 (clock, sin_lookup, Real, temp2);
          mult M3 (clock, sin_lookup, Real, temp3);
          mult M4 (clock, sin_lookup, Imag, temp4);
       end
      end
    end
  endgenerate