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Altera_Forum
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15 years ago

Verilog Error I don't understand

I described this carry select adder ( 2 bits ); module addercs(inu,ind,sum,cy); input [1:0] inu,ind; output [2:0] sum,cy; reg [2:0] sum; reg [2:0] cy; always@(inu or ind) b...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I think your problem is the "#4" in this line of code:

addercs# 4 Report(.inu(ku), .ind(kd), .su(sum), .c(cy));

When instantiating a module, the '#' is used to specify module parameters. But you haven't defined any parameters (only I/Os) So, simply remove the# 4 and I imagine it will compile.

Dan S.