Verilog design and testbench

Ok, now I understand. Basically Verilog syntax is the same for a DUT and testbench. The main difference that if the DUT should be synthesized is written in RTL style. RTL style contains mostly only synthesizable constructs, and a testbench can contain whatever you want.

Generaly a testbench can be recognized that it doesn't have ports, i.e:

module tb ();

It has initial block which cannot exist in the DUT. It has a clock generator which cannot be in the RTL style:

always # 5 clk = ! clk;

And can contain nonsynthesisable tasks as $monitor, $display, $finish etc.