Verilog Compiliation Error

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Hi,

I am also using Quartus 9.0 SP2 but it still comes up as "Can't synthesize current design -- Top partition does not contain any logic".

How do I find out my toplevel? Sorry, i'm pretty new to this stuff. No, not all the code was generated by Megawizard, only the inputs and outputs. The rest are from a website provided by Altera (http://www.altera.com/literature/an/an404.pdf) (http://www.altera.com/literature/an/an404.pdf)

Thanks for your response.

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Hi.

why do you generate only the ports with the Megawizard? I think the code in the application note is only an example to show how it works.

Can you post your Quartus project as a tar-file in the forum ?

Kind regards

GPK