Verilog Compiliation Error

Hi,

I am also using Quartus 9.0 SP2 but it still comes up as "Can't synthesize current design -- Top partition does not contain any logic".

How do I find out my toplevel? Sorry, i'm pretty new to this stuff. No, not all the code was generated by Megawizard, only the inputs and outputs. The rest are from a website provided by Altera (http://www.altera.com/literature/an/an404.pdf) (http://www.altera.com/literature/an/an404.pdf)

Thanks for your response.