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Altera_Forum
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17 years ago

Verilog Compiliation Error

Hi, I am trying to implement a scaling function for the FFT Megacore Function. I copied and modified the Verlilog code from http://www.altera.com/literature/an/an404.pdf. My modified code is at...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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I have modified the code and added in a couple of lines but now, the error is that the "Top partition does not contain any logic". Attached is the new code. Anyone can help me on this? Thanks.

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Hi,

I tried your source code in Quartus project (Quartus 9.0 SP2) and it finished sucessfully.

What was your toplevel when you run your project. BTW your are not using the clk, so get a lot of latches in your design. Is the code generated by the Megawizard ?

Kind regards

GPK