Verilog array assistance

Hello all, I'm attempting to copy a portion of a 128 byte array to a 32 byte array. I'm using one of a possible five 7-bit Addresses to determine the start and end point.

Here are my declarations:

--- Quote Start ---

reg [7:0] STORAGE_BUF0 [31:0];

reg [7:0] LARGE_ARRAY[127:0];

reg [6:0] ADDR [5:0];

--- Quote End ---

Here's where the assignment takes place:

--- Quote Start ---

STORAGE_BUF0[31:0] <= LARGE_ARRAY [(ADDR[0]+7'd32): (ADDR[0]+7'd01)];

--- Quote End ---

The errors I get are:

Error (10133): Verilog HDL Expression error at XX: illegal part select of unpacked array "STORAGE_BUF0"

Error (10734): Verilog HDL error at XX: ADDR is not a constant

Error (10133): Verilog HDL Expression error at XX: illegal part select of unpacked array "LARGE_ARRAY"

Can anyone tell me where I'm messing up?

Thanks in advance!