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Altera_Forum
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16 years ago

Verilog and System Verilog

I came across that System Verilog is extension of Verilog. Does it mean that Verilog is going to replaced by System Verilog for design since all the original features of Verilog is supported by Syst...
Altera_Forum's avatar
Altera_Forum
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16 years ago

SystemVerilog and Verilog do not compare the same as C++ versus C.

First off, there is no "performance" degradation using SystemVerilog as is the (arguable) case with C++.

SystemVerilog adds a number of enhancements to Verilog 2001. Some of these are strictly for simulation (such as Classes), while others work for both simulation and synthesis. Much of the synthesis sub-set is supported under Quartus II, and I highly recommend anyone doing *ANY* Verilog to make themselves aware of some of these new capabilities. Some of the ones I feel deserve particular attention are:

1. New data types (logic is my favorite).

2. Enhancements to the port capabilities (can pass 2D arrays)

3. Enumerated types

4. Packages

5. Interfaces

There are more.. but in my opinion the above items are a minimum that any Verilog developer should learn about. I put them in order, not necessarily of importance, but in terms of how easy they are to start using. Interfaces require some rethinking of your code and styles, but I *strongly* believe they are the single most important enhancement (for synthesis).

The only caveat I can think of to using these new capabilities is that Xilinx does not support them... but, of course, that is one great reason to be using Quartus anyway.

(Last I checked Synpicity supports some or all of the above).

Cheers,

Ed