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Altera_Forum
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15 years ago

Verilog-2001 Variable Declaration With Initialization Synthesis

I wanted to initialize some registers on power up to a default state. I noticed verilog 2001 permits variable declaration with initialization. Like this: reg foo = 1'b1; This is similar t...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I wish I could delete my post. It was documented well in the Quartus handbook. It looks like Quartus also handles any synthesizable initial block statements too.