variable reset simple question

It's not possible to increment the counter and at the same time reset it.

You need to choose your priorities.

clk has priority and OE is read synchronously with one cycle delay:

always @(posedge clkin) begin
     reg OE_D;
     OE_D <= OE;
     if (OE && ~OE_D) begin // synchronously detect rising edge of OE 
          cnt <= 0;
     end else begin
          cnt <= cnt + 1;
     end
end

Otherwise you will need the other version, more economical (only a single register), but does not count up while OE =1

always @(posedge clkin or posedge OE) begin
  if(OE) begin
    cnt <= 0;
  end else begin
    cnt <= cnt + 1;
  end
end

Which tool gives you the error:

"cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct"...

And how exactly did the code that triggered that error looked like ?