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Altera_Forum
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16 years ago

Variable in state Machine going Crazy (VHDL)

OK here is the code for my state machine. I am using it to control a serial multiplier in my circuit/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ent...
Altera_Forum's avatar
Altera_Forum
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16 years ago

It's no reasonable VHDL code. You are implementing a counter in an asynchronous process. That doesn't work. A counter must be implemented in a synchronous process, in other words, it needs an edge sensitive condition to infer registers rather than combinational logic.