Using Simulink for Signal Processing on FPGA

Why would you be asking an Altera based Forum about design work for a Xilinx part?

Interesting?

To answer your question, from my experience, MatLab Simulink generated HDL code is not a efficient as 'good' hand written HDL code.

Now comes the challenging part, how 'good' are you at coding, and simulating?

If writing in a high level in MatLab / Simulink allows you the ability to more efficiently simulate, then explore your options, there might be value in it for you.

You will not be targeting the HDL for the embedded processor in the V2Pro in either case, so I would take a look at the Stratix II or Stratix III offerings if you want more efficient, lower power solutions.

One reporters opinion.

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Why would you be asking an Altera based Forum about design work for a Xilinx part?

Interesting?

To answer your question, from my experience, MatLab Simulink generated HDL code is not a efficient as 'good' hand written HDL code.

Now comes the challenging part, how 'good' are you at coding, and simulating?

If writing in a high level in MatLab / Simulink allows you the ability to more efficiently simulate, then explore your options, there might be value in it for you.

You will not be targeting the HDL for the embedded processor in the V2Pro in either case, so I would take a look at the Stratix II or Stratix III offerings if you want more efficient, lower power solutions.

One reporters opinion.

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Thank you for your reply.

What do you mean by "You will not be targeting the HDL for the embedded processor in the V2Pro in either case" ?

Do you mean that it is not possible to turn a SIMULINK model to an HDL for Virtex 2 Pro 70 ?

THe Virtex II Pro 70 contains both Slices (containing LUTs & FlipFlops), Memory Blocks (and other boolean stuff) and an Embedded Power PC 405 (PPC405) RISC processor.

The MatLab / Simulink models (to the best of my knowledge) generate HDL code which results in LUT & F/F realizations of the structures you are modeling.

I do not think that it will generate "c" code for execution on the embedded PPC processor code in the V2Pro, that is what I am saying (subject to any recent enhancements that I am not aware of).

The code will run just fine in the V2P70, I am just suggesting that you will get better performance and lower power utilizations in the newer Stratix II and Stratix III offerings from Altera.

That's all.:)

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THe Virtex II Pro 70 contains both Slices (containing LUTs & FlipFlops), Memory Blocks (and other boolean stuff) and an Embedded Power PC 405 (PPC405) RISC processor.

The MatLab / Simulink models (to the best of my knowledge) generate HDL code which results in LUT & F/F realizations of the structures you are modeling.

I do not think that it will generate "c" code for execution on the embedded PPC processor code in the V2Pro, that is what I am saying (subject to any recent enhancements that I am not aware of).

The code will run just fine in the V2P70, I am just suggesting that you will get better performance and lower power utilizations in the newer Stratix II and Stratix III offerings from Altera.

That's all.:)

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Thank you for your reply.

We will use the PPC just for management, not for signal processing.

So the HDL will "run" on the FPGA with no help from the PPC.

Our system contains x boards, each contains y FPGAs.

Can we use simulink to simulate such system ?

Thanks.

Given the above clarity, Yes.

I am still wondering why you would be asking an Altera based Forum about design work for a Xilinx part? Seems rather rude, like asking for VHDL help in a Verilog Forum, or ADA coding help in a "C" code forum. Just wondering.

Good luck with the project.