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Why would you be asking an Altera based Forum about design work for a Xilinx part?
Interesting?
To answer your question, from my experience, MatLab Simulink generated HDL code is not a efficient as 'good' hand written HDL code.
Now comes the challenging part, how 'good' are you at coding, and simulating?
If writing in a high level in MatLab / Simulink allows you the ability to more efficiently simulate, then explore your options, there might be value in it for you.
You will not be targeting the HDL for the embedded processor in the V2Pro in either case, so I would take a look at the Stratix II or Stratix III offerings if you want more efficient, lower power solutions.
One reporters opinion.
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Thank you for your reply.
What do you mean by "You will not be targeting the HDL for the embedded processor in the V2Pro in either case" ?
Do you mean that it is not possible to turn a SIMULINK model to an HDL for Virtex 2 Pro 70 ?
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