Hi all, I'm rather new to FPGA development, and Im having trouble finding a megafunction for the SDRAM for my DE2. I see there is something for it in the SOPC builder, but that's no help to me as far as I can tell. Im a little confused that there is nothing included from Altera for this purpose. What would you do to instantiate an SDRAM controller? Thanks, - John

Hi, I have the same problem, I read the datasheed of the SDRAM and found the State Machine Diagram very confusing (and hard to implement). You can try to make your own function to control the SDRAM following that diagram, but you have to be very careful with times... Also, I found somewhere on Altera's web page (can't remember where) a function that someone else did, didn't try it myself, but maybe that's the solution. I hope it helps.. :)

Maybe I should clarify a bit. I am a masters student attempting to implement some algorithms on the FPGA as part of a research project. Large data vectors are involved, which leaves me with no choice but to use the SDRAM memory on the DE2 board. Is there a simple way to instantiate a controller for this? Google isn't helping out too well. :) 8MB (1M x 16bit x 4 banks) 2-2-2 100MHz SDRAM

Sorry, I didn't see your post before I posted again. Thanks for the reply. Building my own controller is out of my experience. I've found a few controllers, but they have to be edited to work with the DE2. Im coming at this from a software background, so thats going to take me a while to figure out. I was hoping that, since it is an educational development board, there would be a simple way get a controller onto it.

Humm.. they say that you can instantiate the controller with SOPC or NIOS II (a friend was succesful using the SDRAM with NIOS II) but you have to change the default data width.. Maybe this helps: http://www.altera.com/education/univ/materials/boards/unv-de2-board-faq.html http://www.altera.com/education/univ/materials/manual/labs/tut_de2_sdram_vhdl.pdf http://www.altera.com/education/univ/materials/manual/labs/tut_de2_sdram_verilog.pdf I'm reading the first pdf (at bottom) of this page: http://www.altera.com/products/ip/iup/memory/m-alt-ddr2_sdram.html and it's very interesting.. :) I think there's a solution.. Hope It helps

I searched Altera's site too :p I think the DDR megafunctions are no good for the SDRAM. Don't want the NIOS, i'll be implementing the algorithms as hardware circuits. You think it would work if I created the NIOS with an SDRAM controller in the SOPC builder, then use the VHDL code for the memory controller which the SOPC builder spits out?

Using SDRAM on a DE2 | Altera Community

14 Replies

Altera_Forum
Honored Contributor
18 years ago
Yes, I took a look at that controller. It was hard to understand how to use it, since there is little to no documentation with it. I've never worked with SDRAM at such a low level before, so I need to keep it simple :P

The reference controller looks as if it will work fine for my purposes, and the whitepaper that comes with it is very informative. I may even rewrite it a little, since I will only be using page bursts (so as to maximize the throughput).
Altera_Forum
Honored Contributor
18 years ago
All,

Altera provides a library of SOPC Builder components (IP cores), which are listed in the URL below, for all I/O devices on the DE1 and DE2 boards. These components can be used as part of the SOPC Builder tool in the Quartus® II software. They allow users to easily create Nios® II systems that can access the I/O devices on the DE1 and DE2 boards. Also provided are the associated software drivers that can be incorporated into an Altera® Debug Client project (or an Altera Nios II IDE project).

http://www.altera.com/education/univ/ip-cores/unv-ip-cores.html

--jmv
Altera_Forum
Honored Contributor
18 years ago
The SOPC Builder core is here: http://www.altera.com/education/univ/ip-cores/unv-ip-cores.html

Thanks,

--Steve
Altera_Forum
Honored Contributor
18 years ago
The DE2 kit should come with a CD full of demonstrations. The demo titled "DE2_TV" utilizes a 4-port SDRAM controller, which isn't generated by the SOPC. I've been using it the same situation you seem to be looking for (hardware circuits, no NIOS processor).

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Using SDRAM on a DE2

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