Honored ContributorHi all,
I'm rather new to FPGA development, and Im having trouble finding a megafunction for the SDRAM for my DE2. I see there is something for it in the SOPC builder, but that's no help to me as far as I can tell. Im a little confused that there is nothing included from Altera for this purpose. What would you do to instantiate an SDRAM controller? Thanks, - John
Honored ContributorHi, I have the same problem, I read the datasheed of the SDRAM and found the State Machine Diagram very confusing (and hard to implement).
You can try to make your own function to control the SDRAM following that diagram, but you have to be very careful with times... Also, I found somewhere on Altera's web page (can't remember where) a function that someone else did, didn't try it myself, but maybe that's the solution. I hope it helps.. :)Honored ContributorMaybe I should clarify a bit. I am a masters student attempting to implement some algorithms on the FPGA as part of a research project. Large data vectors are involved, which leaves me with no choice but to use the SDRAM memory on the DE2 board. Is there a simple way to instantiate a controller for this? Google isn't helping out too well. :)
8MB (1M x 16bit x 4 banks) 2-2-2 100MHz SDRAMHonored ContributorSorry, I didn't see your post before I posted again. Thanks for the reply.
Building my own controller is out of my experience. I've found a few controllers, but they have to be edited to work with the DE2. Im coming at this from a software background, so thats going to take me a while to figure out. I was hoping that, since it is an educational development board, there would be a simple way get a controller onto it.Honored ContributorHumm.. they say that you can instantiate the controller with SOPC or NIOS II (a friend was succesful using the SDRAM with NIOS II) but you have to change the default data width..
Maybe this helps: http://www.altera.com/education/univ/materials/boards/unv-de2-board-faq.html http://www.altera.com/education/univ/materials/manual/labs/tut_de2_sdram_vhdl.pdf http://www.altera.com/education/univ/materials/manual/labs/tut_de2_sdram_verilog.pdf I'm reading the first pdf (at bottom) of this page: http://www.altera.com/products/ip/iup/memory/m-alt-ddr2_sdram.html and it's very interesting.. :) I think there's a solution.. Hope It helpsHonored ContributorI searched Altera's site too :p I think the DDR megafunctions are no good for the SDRAM.
Don't want the NIOS, i'll be implementing the algorithms as hardware circuits. You think it would work if I created the NIOS with an SDRAM controller in the SOPC builder, then use the VHDL code for the memory controller which the SOPC builder spits out?Honored ContributorHonored ContributorThanks, that looks promising. Unfortunately the code files will not download, although maybe they will later on. ftp.altera.com seems to be down right now.
Honored ContributorI can't really make sense of the controller generated by the sopc builder. It's not documented very well.
I still cannot connect to the reference controller at ftp.altera.com either... Seems to be exactly what i am looking for though. I can't start work on the rest of the project until I have an controller to use either. If anyone can connect to it, https://www.altera.com/servlet/download?swcode=www-ref-ssc-11-pc-vhdl&referer=https://www.altera.com/support/software/download/refdesigns/sdram-controller/dnl-sdr-sram.jsp I would really appreciate it if you could email it to me.Honored ContributorThank you Enrique! It looks good, I think this will do nicely. Thanks to Bee Gee A for finding it to begin with too :)
Honored ContributorHi, I don't have a DE2 board, but I assume you can just use the generic Altera SDRAM controller which comes with the niosii eds (https://www.altera.com/support/software/download/nios2/dnl-nios2.jsp), have you tried that?
Even with the evaluation version of the NiosII EDS, the SDRAM controller is fully working and not limited in any way.
