Forum Discussion
Honored ContributorUsing SDRAM on a DE2
Hi all,
I'm rather new to FPGA development, and Im having trouble finding a megafunction for the SDRAM for my DE2. I see there is something for it in the SOPC builder, but that's no help to me as far as I can tell. Im a little confused that there is nothing included from Altera for this purpose. What would you do to instantiate an SDRAM controller? Thanks, - John14 Replies
Altera_ForumThe DE2 kit should come with a CD full of demonstrations. The demo titled "DE2_TV" utilizes a 4-port SDRAM controller, which isn't generated by the SOPC. I've been using it the same situation you seem to be looking for (hardware circuits, no NIOS processor).
- Altera_Forum
The SOPC Builder core is here: http://www.altera.com/education/univ/ip-cores/unv-ip-cores.html
Thanks, --Steve - Altera_Forum
All,
Altera provides a library of SOPC Builder components (IP cores), which are listed in the URL below, for all I/O devices on the DE1 and DE2 boards. These components can be used as part of the SOPC Builder tool in the Quartus® II software. They allow users to easily create Nios® II systems that can access the I/O devices on the DE1 and DE2 boards. Also provided are the associated software drivers that can be incorporated into an Altera® Debug Client project (or an Altera Nios II IDE project). http://www.altera.com/education/univ/ip-cores/unv-ip-cores.html --jmv - Altera_Forum
Yes, I took a look at that controller. It was hard to understand how to use it, since there is little to no documentation with it. I've never worked with SDRAM at such a low level before, so I need to keep it simple :P
The reference controller looks as if it will work fine for my purposes, and the whitepaper that comes with it is very informative. I may even rewrite it a little, since I will only be using page bursts (so as to maximize the throughput). - Altera_Forum
Hi, I don't have a DE2 board, but I assume you can just use the generic Altera SDRAM controller which comes with the niosii eds (https://www.altera.com/support/software/download/nios2/dnl-nios2.jsp), have you tried that?
Even with the evaluation version of the NiosII EDS, the SDRAM controller is fully working and not limited in any way. - Altera_Forum
Thank you Enrique! It looks good, I think this will do nicely. Thanks to Bee Gee A for finding it to begin with too :)
- Altera_Forum
I can't really make sense of the controller generated by the sopc builder. It's not documented very well.
I still cannot connect to the reference controller at ftp.altera.com either... Seems to be exactly what i am looking for though. I can't start work on the rest of the project until I have an controller to use either. If anyone can connect to it, https://www.altera.com/servlet/download?swcode=www-ref-ssc-11-pc-vhdl&referer=https://www.altera.com/support/software/download/refdesigns/sdram-controller/dnl-sdr-sram.jsp I would really appreciate it if you could email it to me. - Altera_Forum
Thanks, that looks promising. Unfortunately the code files will not download, although maybe they will later on. ftp.altera.com seems to be down right now.
- Altera_Forum
- Altera_Forum
I searched Altera's site too :p I think the DDR megafunctions are no good for the SDRAM.
Don't want the NIOS, i'll be implementing the algorithms as hardware circuits. You think it would work if I created the NIOS with an SDRAM controller in the SOPC builder, then use the VHDL code for the memory controller which the SOPC builder spits out?
