using memory ram in cycloneII

Question

Hi! What is the verilog code to tell the compiler to use the internal RAM chip?   reg[7:0]  ram[1024];

altera_forum · Answer

take a look at the Verilog templates in Quartus II under Edit &gt; Insert Template

altera_forum · Answer

tnx!

is it correct?

module ram(clk,data,myaddr,myram);

input clk;

input[7:0] data;

input[9:0] myaddr;

output[7:0] myram;

reg[7:0] myram[1023:0];

always@(posedge clk)

myram[myaddr]<=data;

endmodule

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