Using megafunction vs just Verilog expression

I guess the megafunction would be the most optimised code, having the choice of pipelining. You can open the .v file and see what optimisations they implement. I guess that a MF multiplier would also take care of some exceptional cases such as multiplying infinity and such.

A HDL multiply expression basically infers the same MegaFunction IP. But you don't have some of the options to control e.g. pipeling. For multipliers, the default is mostly O.K., so you don't need it.

if you're using multipliers wider than 18 bits you'll want to use the Megafunction and add some pipelining if fmax is of concern.