Using MAX V Parallel Flash Loader to configure Xil Artix
I have an already existing project containing Arria V FPGA (with NIOS II soft processor) and a MAX V CPLD as a system controller. In this system an external flash memory is attached to the MAX V containing configuration data of Arria V which is loaded into it by the PFL IP. Arria V has an Ethernet connection where it can receive new configuration image and update the MAX V external flash memory.
Now I have to add a new resource-demanding IP which supports Xil devices only so I have to add 2x Artix Ultrascale+ FPGAs to the board. They have to be configured from the same MAX V so the flash memory should contain their images and PFL should perform configuration as well.
I found raw configuration data (.bin file) could be converted to Intel hex format and added to the flash image. So pof could be generated. But when it is in the flash/MAX V subsystem, how will it start to load to the Artix FPGAs?
Could this idea work? Do you have any experience with such arrangement?