G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ??? hope someone can help me greets !!!

What ADC, I mean can you give us the Partnumber?

hey.. it´s analogs ad9252 thanks

The serialisation factor in your system is actually 14. The ALTLVDS does not support this, but you could set it to handle a deserialisation of 7 bits and concatenate two 7-bit packets into one 14 bit. ALTLVDS however uses a PLL to sample the inputs, so if you have multiple devices, ADCs in this case) you may run out of PLLs. However as the outputs of the ADC are nicely source synchronous and are accompanied by a dataclock and a frame-indicator , you can easily deserialise the ADC data channels with simple shiftregisters. Feed the inputs into a DDR-In block and then serialise the 2 bits in a 7-bit shiftregister each. assemble the 2 7-bit buses into a 14-bit bus and define the right moment to register it. You need to do some work to constrain all this though. I have done this for ADS527x and AD9222 octal ADCs, unfortunately my code is in AHDL (I do use VHDL nowadays).

Hi there !!! Are u sure about the value of the serialisation factor? I thought that a serialisationfactor unequal one is only possible if i would mix, say 2 channels, together and transfer the data alternating. so for mixing 2 channels gives an serialisationfactor or deserialisationfactor of 2, so every second bit (beginning with bit 0) belongs to channel 1 and all other to channel 2. So it doesn´t matter how many bits belong to one datastream or sampled value. I´m not sure about but i thought that i found this out while reading through altlvds documentation. The problem with running out of PLL came also to my mind as i will use more devices so i think i´ll have to find ways to work without the megafunction and use the dataclock and frame-indicator in combination with shiftregisters... So the solution u provided in your previous post is this possible solution using altlvds or not ? what´s this ddr-in block ? Is it possible to go in shiftregisters with differential signals ?? thanks for helping greets

AD9252 is basically similar to AD9222, expect for a resolution of 14 versus 12 bit. I completely agree with josyb about the suggested solution (DDIO + shift register). Also the deserialization factor of 14 is correct. Strictly spoken, you won't necessarily need a PLL for the receiver, because the ADC provide both fast and slow (respectively bit and frame) clock. but, 700 Mbps is pretty on the edge, a means to adjust the clock phases manually may turn out to be badly required. A receiver PLL would use the frame clock (FCO) as input clock and generate the fast clock. You can also connect both ADC clocks to the FPGA and keep all options. See below a VHDL example of 4-channel 14-Bit ADC receiver, that can be easily changed to 8 Channels. chan: FOR I IN 0 TO 3 GENERATE lvds_rcv : altddio_in GENERIC MAP ( intended_device_family => "Cyclone III", invert_input_clocks => "ON", lpm_type => "altddio_in", power_up_high => "OFF", width => 1 ) PORT MAP ( datain => AD9259_D(I DOWNTO I), inclock => fastclock, dataout_h => dataout_h(I DOWNTO I), dataout_l => dataout_l(I DOWNTO I) ); PROCESS (fastclock) BEGIN IF rising_edge(fastclock) THEN lvds_sr(I) <= lvds_sr(I)(11 downto 0) & dataout_l(I) & dataout_h(I); END IF; END PROCESS; PROCESS (slowclock) BEGIN IF reset = '1' THEN lvds_rx(I) <= (others => '0'); ELSIF rising_edge(slowclock) THEN lvds_rx(I) <= lvds_sr(I); END IF; END PROCESS; END GENERATE;

using lvds | Altera Community

45 Replies

Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
1) I'm not a Stratix expert, so I would need to study this further, but this is outside my scope. Perhaps somebody else will answer this question?
2) The DCO clocks (and data) go to the EP2C8 devices, as the EP2SGX60 didn't have enough LVDS Receivers. From the EP2C8's I have 4 wide-parallel LVCMOS buses feeding into the EP2SGX60.
3) You still didn't tell which Stratix IV device you are targeting? Although I have to repeat I'm not a Stratix expert at all. With 12 ADC devices you will need 12 * 6 or 96 LVDS inputs in total, and 12 of them need to feed into a clock input. Achieving timing closure at 1000 Mbps, using static .sdc constraints, may turn out to be difficult. And using the DPA feature in the ALTLVDS may then be a better approach.

I balanced all timing delays. On the picture the analog data is fed in from the right going left, I also fed the ADC clocks first going from the EP2SGX60 FPG to the far right and then horizontally feeding 4 ADCs. As such all analog signals are sampled at the same moment. The digital signals all reach their respective EP2C8 at the same time, but this is not essential as they are source synchronous signals.

Regards,

Josy
--- Quote End ---

Hi Josy,

1. My FPGA part is EP4SGX230KF40C4.
2. If i use ALTLVDS megafunction, my fpga doesn't support 12 ALTLVDS modules. There are toal 4 altlvds module in EP4SGX230KF40.
3. Can the DDIO decrease the speed from 1000Mbps to 500Mbps after the ADC data come into FPGA? If this is the case, the register shift will run at 500MHz in logic.

BTW, I have a thought, however, i don't know if this can be implemented. You know, i will group 3 or 4 AD9633 into a group. So can i only connect one of the group's ADCs DCO to fpga, and process them by using one ALTLVDS module as the attaced image shows. Then i can receive all 12 AD9633 by 4 altlvds modules. The key issue is if DCO connected to fpga synchronizes with other ADCs output data? If not, the logic design will lose relationship between clock and data. I can carefully route the clock trace to all ADC, and ensure their lengh to be equal.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13055&stc=1
Altera_Forum
Honored Contributor
9 years ago
I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
Hi Josy,

1. My FPGA part is EP4SGX230KF40C4.
2. If i use ALTLVDS megafunction, my fpga doesn't support 12 ALTLVDS modules. There are toal 4 altlvds module in EP4SGX230KF40.
3. Can the DDIO decrease the speed from 1000Mbps to 500Mbps after the ADC data come into FPGA? If this is the case, the register shift will run at 500MHz in logic.

BTW, I have a thought, however, i don't know if this can be implemented. You know, i will group 3 or 4 AD9633 into a group. So can i only connect one of the group's ADCs DCO to fpga, and process them by using one ALTLVDS module as the attaced image shows. Then i can receive all 12 AD9633 by 4 altlvds modules. The key issue is if DCO connected to fpga synchronizes with other ADCs output data? If not, the logic design will lose relationship between clock and data. I can carefully route the clock trace to all ADC, and ensure their lengh to be equal.

--- Quote End ---

Hi Jerry,

I did some more study, and I believe you can have your cake and eat it :)
IMHO it can work as you describe / have drawn. Almost, as you will have to feed one FCO clock instead of one DCO clock (per group of 3 aggregated ADCs). The ALTVDS PLL requires the base clock as input.
https://www.alteraforum.com/forum/attachment.php?attachmentid=13057
The FCO clocks of the three ADCs in each block will run at (exactly) the same frequency, but with an unknown phase-shift. But this phase-shift doesn't matter as the DPA circuitry in the receiver datapath will select the best phase for each data signal.
It could be advantageous if you can match the trace lengths per group of 3 ADCs. The four groups can have quite different trace lengths. Also don't over-strain your self with matching the lengths between signals; 50 ps is about 7 mm trace length.
Although IMHO it won't matter, the DPA will select the phase of the PLL clock to sample within 1/16 of the UI (or 62.5 ps in your case) of the ideal position.

I would be careful though and also seek advice from the other Experts (FvM, Tricky, ... ?) too.

Regards,
Josy
multiple-attachments.zip31 KB
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output.
--- Quote End ---

Yes, column I/O LVDS pins would also be one of the solutions for our case. However, our system still use many normal I/O pins to interface other parts. So i have to group several ADC devices to save I/O pins resource.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
Hi Jerry,

I did some more study, and I believe you can have your cake and eat it :)
IMHO it can work as you describe / have drawn. Almost, as you will have to feed one FCO clock instead of one DCO clock (per group of 3 aggregated ADCs). The ALTVDS PLL requires the base clock as input.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13057&stc=1
The FCO clocks of the three ADCs in each block will run at (exactly) the same frequency, but with an unknown phase-shift. But this phase-shift doesn't matter as the DPA circuitry in the receiver datapath will select the best phase for each data signal.
It could be advantageous if you can match the trace lengths per group of 3 ADCs. The four groups can have quite different trace lengths. Also don't over-strain your self with matching the lengths between signals; 50 ps is about 7 mm trace length.
Although IMHO it won't matter, the DPA will select the phase of the PLL clock to sample within 1/16 of the UI (or 62.5 ps in your case) of the ideal position.

I would be careful though and also seek advice from the other Experts (FvM, Tricky, ... ?) too.

Regards,
Josy
--- Quote End ---

Hi Josy,

Thanks for you reply me so quickly.

This is the first time we use serial LVDS ADC devices in our applications, our previous ADC parts are AD9218 and AD9288. So i need study more and think more before we finish hardware schematic design. Your comments make me more confident. Is it better that use DCO as clock and FCO as word edge indicator? As lvds pins are enough for my case, and each ADC's FCO may be connected to FPGA.

Furthermore, what is the skew effect among ADC devices in one group? I don't know if the convertion delay is consistent among differnet ADC devices? I don't worry about this among channels inside one ADC device.

Actually, i'm study TI's ADS52J90 datasheet during i studying AD9633 (and AD9681, which must use 2-lane, will consume more lvds lines, and pass). Question is the input BW of ADS52J90 is only 70MHz.

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using lvds

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