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Altera_Forum
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15 years ago

using lvds

G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This seri...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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1) I'm not a Stratix expert, so I would need to study this further, but this is outside my scope. Perhaps somebody else will answer this question?

2) The DCO clocks (and data) go to the EP2C8 devices, as the EP2SGX60 didn't have enough LVDS Receivers. From the EP2C8's I have 4 wide-parallel LVCMOS buses feeding into the EP2SGX60.

3) You still didn't tell which Stratix IV device you are targeting? Although I have to repeat I'm not a Stratix expert at all. With 12 ADC devices you will need 12 * 6 or 96 LVDS inputs in total, and 12 of them need to feed into a clock input. Achieving timing closure at 1000 Mbps, using static .sdc constraints, may turn out to be difficult. And using the DPA feature in the ALTLVDS may then be a better approach.

I balanced all timing delays. On the picture the analog data is fed in from the right going left, I also fed the ADC clocks first going from the EP2SGX60 FPG to the far right and then horizontally feeding 4 ADCs. As such all analog signals are sampled at the same moment. The digital signals all reach their respective EP2C8 at the same time, but this is not essential as they are source synchronous signals.

Regards,

Josy

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Hi Josy,

1. My FPGA part is EP4SGX230KF40C4.

2. If i use ALTLVDS megafunction, my fpga doesn't support 12 ALTLVDS modules. There are toal 4 altlvds module in EP4SGX230KF40.

3. Can the DDIO decrease the speed from 1000Mbps to 500Mbps after the ADC data come into FPGA? If this is the case, the register shift will run at 500MHz in logic.

BTW, I have a thought, however, i don't know if this can be implemented. You know, i will group 3 or 4 AD9633 into a group. So can i only connect one of the group's ADCs DCO to fpga, and process them by using one ALTLVDS module as the attaced image shows. Then i can receive all 12 AD9633 by 4 altlvds modules. The key issue is if DCO connected to fpga synchronizes with other ADCs output data? If not, the logic design will lose relationship between clock and data. I can carefully route the clock trace to all ADC, and ensure their lengh to be equal.

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