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Hi Jerry,
I did some more study, and I believe you can have your cake and eat it :)
IMHO it can work as you describe / have drawn. Almost, as you will have to feed one FCO clock instead of one DCO clock (per group of 3 aggregated ADCs). The ALTVDS PLL requires the base clock as input.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13057&stc=1 The FCO clocks of the three ADCs in each block will run at (exactly) the same frequency, but with an unknown phase-shift. But this phase-shift doesn't matter as the DPA circuitry in the receiver datapath will select the best phase for each data signal.
It could be advantageous if you can match the trace lengths per group of 3 ADCs. The four groups can have quite different trace lengths. Also don't over-strain your self with matching the lengths between signals; 50 ps is about 7 mm trace length.
Although IMHO it won't matter, the DPA will select the phase of the PLL clock to sample within 1/16 of the UI (or 62.5 ps in your case) of the ideal position.
I would be careful though and also seek advice from the other Experts (FvM, Tricky, ... ?) too.
Regards,
Josy
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Hi Josy,
Thanks for you reply me so quickly.
This is the first time we use serial LVDS ADC devices in our applications, our previous ADC parts are AD9218 and AD9288. So i need study more and think more before we finish hardware schematic design. Your comments make me more confident. Is it better that use DCO as clock and FCO as word edge indicator? As lvds pins are enough for my case, and each ADC's FCO may be connected to FPGA.
Furthermore, what is the skew effect among ADC devices in one group? I don't know if the convertion delay is consistent among differnet ADC devices? I don't worry about this among channels inside one ADC device.
Actually, i'm study TI's ADS52J90 datasheet during i studying AD9633 (and AD9681, which must use 2-lane, will consume more lvds lines, and pass). Question is the input BW of ADS52J90 is only 70MHz.
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