Forum Discussion
JC48
New Contributor
New ContributorUsing f2sdram ports of Stratix 10 HPS
I have a design where I need to write data from the HPS to some FPGA cores, which spits output to get sent back to the f2sdram0 data port of the HPS. For simple debugging I simply have an Intel AXI...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
Firstly, I would want to make sure the bridges are enabled properly,
Bridge configuration for Stratix 10 can be found here:
https://rocketboards.org/foswiki/Documentation/S10SoCBridgeConfiguration
Regards.
EBERLAZARE_I_IntelRegular Contributor
Regular ContributorHi,
Do you have any followup from your side?
Regards.
