using epcs flash for both reset vector and store configuration

If you look through the HAL sources you'll find the low level functions that actually do the read/write/erase actions (by driving the SPI block).

You should be able to compile those files and then directly call the functions.

The smallest fpga resource use probably comes from defining an avalon slave that directly accesses the epcs SPI signals and then directly bit-bashing them.

The SPI interface hardware might be faster for reads, but for writes and erases the time spent waiting for the operation to complete dominates.

Some quick design (assuming little-endian data):

struct spi_bang {
    volatile uint32_t spi_data_low:  /* write low bit with clock low. */
    volatile uint32_t spi_data_high; /* write low bit with clock high. */
    volatile uint32_t spi_control;   /* chip select etc.*/
    volatile uint32_t spi_pad;
};

Then you write the same value to spi_data_low, spi_data_high and spi_data_low again before shifting right one bit and looping through the required number of bits.

With a 100MHz nios and assuming two clocks for each Avalon write an unrolled loop would need 7 clocks per byte - 14MHz.