New Contributor
Regular ContributorHi,
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf (Page 40), you have to create the virtual clock with the same period and phase shift as the real clock in the source device, which means that the following two constraints need to have same phase shift.
create_clock -name {ADC_DCLK_Input} -period 3.333 -waveform { 0.833 2.5 } [get_ports {ADC3224_DCLK_In}]
create_clock -name {ADC_VirtualClk} -period 3.333
Thanks.
New ContributorHi YY,
Thanks for reply. In my understanding and according to ADC3224 data sheet(page 45), data are clocked out 90 degrees prior the rising and falling edge of DCLK.
Waveform below is the output timing diagram of ADC3224 in x6 mode, and the green signal is the virtual clock I added to described the clock of ADC output registers.
In my application, Frame Clock(FCLK) runs at 100MHz and therefore both virtual and actual output clock of ADC are set as 300MHz in SDC.
Therefore I think it's more like the definition "Case 2: The FPGA is the receiver and does not phase-shift the clock" in Ryan Scoviller's writing, "Source-Synchronous Timing with TimeQuest".
That's why in my SDC I described a 90 degrees(0.833 ns) phase shift on ADC_DCLK_Input, instead of making ADC_DCLK_Input and ADC_VirtualClk having the same phase shift.
Should I have any misunderstanding, please let me know.
Thanks,
