Altera_Forum
Honored Contributor
Honored ContributorUsing cyclone iv E device as clock source
i wonder if it's realistic to implement a low-jitter( <10 ps ) differential (LVDS, LVPECL, etc.)clock source with the EP4CE6 FPGA.
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Altera_ForumHonored Contributor
Honored ContributorCheck the handbook. It will have jitter specs for the PLLs. My guess would be no, you can't.
