Honored ContributorIf u r using
type is array (.. to ..) of std_logic_vector (.. downto ..)
Honored ContributorAn array is just an array. How you access it affects whether the synthesisor implements a dual ported ram or not. If you follow the coding guidlines, then it will place a ram block for you. If you break these guidelines, it will implement it in logic (and eat your device up).
If the array that is accessed is a contant, it will place a rom, if the array is a signal or shared variable, it places a ram. If you do two reads and two writes to the array in a single clock cycle, its dual ported, else single ended.Honored Contributori'm using the array as a followed:
In one cycle. If the input data is greater than the value in the array -> overwrite array. Compiler gives the warnig that aditional logic is being added because of the read and write action in one cycle. Is this single ended or dual ported. I'm confused because of the two actions, but to the same adress.Honored Contributorreading and writing to the same address usually isnt possible in the same cycle, or if it is, you have to use the ram asynchronously which Im not sure is possible with all devices. Using it asynchronously will reduce your FMAx.
If you are reading and writing, usually you read in 1 clock, and write back in the next (while simultaneously reading the next address).Honored ContributorSo a write to one adress + a read from anothers adress is possible with single ended ?
Thx for your effort!Honored ContributorHaving two addresses means dual port.
Honored ContributorHere is a question: How to place my 2-d array,which is signal,writable and readable, into a flash memory?
Board Info: Nios II Cy2 ep2c35 Thanks in advance.
