Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorUsing array
If u r using type is array (.. to ..) of std_logic_vector (.. downto ..)
How do u know its single ended, dual ported , .... ? Or is the best way to program with Insert templates or me...
Altera_ForumHonored Contributor
Honored ContributorAn array is just an array. How you access it affects whether the synthesisor implements a dual ported ram or not. If you follow the coding guidlines, then it will place a ram block for you. If you break these guidelines, it will implement it in logic (and eat your device up).
If the array that is accessed is a contant, it will place a rom, if the array is a signal or shared variable, it places a ram. If you do two reads and two writes to the array in a single clock cycle, its dual ported, else single ended.
