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Altera_Forum's avatar
Altera_Forum
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12 years ago

using altera FPL and choosing the configuration file in real time

hi,

im using the altera pfl.

the external flash stores 4 different configuration files.

the flash is connecterd to max II cpld that responsible for the fpga configuration.

my question is how can the cpld control on which file is going to be load to the fpga.

best regards,

or shoshani

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Your question is not really complete enough. What hardware platform are you using?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Your question is not really complete enough. What hardware platform are you using?

    --- Quote End ---

    im using custom hardware, the hardware consists of :

    External cpu,

    ArriaV gx FPGA ,

    Max II cpld

    512 mb parallel spansion flash,

    the flash is connected to the max II cpld , the the CPLD is connected to the configuration pins of the Arria.

    i whould like to store 4 different FPGA configuration files in the flash . and the cpu through the cpld can choose which configuration file is going to be loaded to the fpga.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You need to provision the bottom boot address into the CPLD before you initiate the FPGA boot. Assuming you have some connections from the cpu to the CPLD then you can use these to indicate which boot image to use. Alternatively, you may have jumpers connected to the CPLD with which you can specify the image you wish to boot the FPGA with. Either way, you will have to write some code for the CPLD to interpret the cpu signals or jumpers and provision one of four boot addresses.

    The CPLD will then read the data directly from the FLASH, starting from your provisioned base address, delivering the bitstream to the FPGA via the configuration pins.

    Regards,

    Alex