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Honored Contributor
Honored ContributorUsing a PLL to synchronize two clocks
Hello, I have a 120 MHz external clock entering the FPGA (Stratix II). Part of the interface in the FPGA must work at the 120 MHz, but most of it (including a Nios CPU) works at 60 MHz. The 60 ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes, create a PLL with two outputs of 120Mhz and 60MHz. Everything will be taken care of for you. No reason to do Zero Delay Buffer either, and you can leave it in Normal mode. --- Quote End --- So the two clocks generated by the same PLL and are a multiple of one another (two of C1..C6, IIRC) are guaranteed to be phase aligned? Does the PLL have to be enhanced for that, or will a fast PLL do the same?
