User POR?

Its pretty common for the development kits to have push-buttons, some even label the net for one of the push-buttons as cpu_rstN.

You can code HDL without a reset source, you just have to make sure you initialize the signals correctly, eg.,

signal count : unsigned(WIDTH-1 downto 0) := (others => '0');
...
process
begin
    if rising_edge(clk) then
        count <= count + 1;
    end if;
end process;

The FPGA/CPLD configuration image will implement that initial condition.

Cheers,

Dave

Push button won't do - must be automatic at every power-on. And initializing the count in the HDL doesn't mean that the FPGA will do the same thing on power up. Simulators also have their own ideas of what the initial state of the flip-flops may be. In the Quartus 9.1 Waveform Simulator that I am using, all flip-flops are assumed unknown state during initialization. Attempting to connect the flip-flop CLRN and PRN inputs to VCC generates warnings that the output is stuck.

The attached circuit simulates correctly. The flip-flops are initialized to LOW by the default state of the input pin at VCC and the following inverter, but the pin is connected to GND externally. After the FPGA initializes, the pin is connected to the external GND, thereby releasing the flip-flops to begin counting. The POR signal has a duration of at least 1 clock period, and drives an output green LED on the board to indicate when it is released.

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Push button won't do - must be automatic at every power-on.

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Ok.

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And initializing the count in the HDL doesn't mean that the FPGA will do the same thing on power up.

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It depends how close to "the same thing" you want.

An initial value in the HDL is stored in the configuration file, so a '0' will be a zero, and a '1' will be a one. What you cannot do is use this initial value to "enable" a state machine or controller, since the clock will power-on at an arbitrary time. What you need to do in that case is to start a counter at power-on. The "enable" to that counter has to go through a synchronizer so that the enable signal asserts synchronous to the clock. That enable can then count-down the counter until zero. The carry-out from that counter can be used as your power-on reset. The reset will synchronously deassert, and it will repeatable at power-on (ignoring the synchronizer metastable delay variations).

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Simulators also have their own ideas of what the initial state of the flip-flops may be. In the Quartus 9.1 Waveform Simulator that I am using, all flip-flops are assumed unknown state during initialization. Attempting to connect the flip-flop CLRN and PRN inputs to VCC generates warnings that the output is stuck.

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That is not a "real" simulator. Use Modelsim.

Cheers,

Dave

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My schematic picture is exactly the enable and synchronizer that you describe. The only difference is that my enable is external because the schematic and waveform simulator do not provide the internal initialization capability that you have in HDL.

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Hey, you said you a push-button would not do! :)

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And yes, it is true that the FPGA will initialize the hardware as specified by the HDL. Haven't tried this in ModelSim, but if it recognizes the initialization code then it can resolve the startup conditions

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Modelsim implements the initialization correctly.

Cheers,

Dave