User POR?

Push button won't do - must be automatic at every power-on. And initializing the count in the HDL doesn't mean that the FPGA will do the same thing on power up. Simulators also have their own ideas of what the initial state of the flip-flops may be. In the Quartus 9.1 Waveform Simulator that I am using, all flip-flops are assumed unknown state during initialization. Attempting to connect the flip-flop CLRN and PRN inputs to VCC generates warnings that the output is stuck.

The attached circuit simulates correctly. The flip-flops are initialized to LOW by the default state of the input pin at VCC and the following inverter, but the pin is connected to GND externally. After the FPGA initializes, the pin is connected to the external GND, thereby releasing the flip-flops to begin counting. The POR signal has a duration of at least 1 clock period, and drives an output green LED on the board to indicate when it is released.