User data in CFI flash via MAX2

Is this a custom Stratix IV GT board, or an Altera Development Kit?

Conceptually the MAX II configuration could be designed to operate in FPP mode at power-on, and then switch over to a bridge mode, where it provided access to the Flash via the Stratix IV GT FPP data bus. Unfortunately there are only 8-bits on that bus, so you'd have to come up with a protocol for the 8-bits to indicate read-to-flash and write-to-flash. This is not that difficult, in that examples of this type of protocol already exist, eg., see the JTAG-to-Avalon-ST bridge protocol

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf

Unfortunately this bridge logic does not "come for free", so if your MAX II is already 100% used with a PFL configuration controller, there won't be any space for your bridge logic :(

If you have a schematic for the board, I can take a look, and could provide other suggestions.

Cheers,

Dave