usedw signal in scififo

I used Modelsim to do the simulation, and see all the signals in the fifo, and only see one bit of usedw:), even I define the wire connected to usedw to be 5 bits

Is there anything wrong? I attached figure of modelsim simulation

the selected codes are:

...

parameter DATAWIDTH = 32;

parameter MAXBURSTCOUNT = 4;

parameter BURSTCOUNTWIDTH = 3;

parameter BYTEENABLEWIDTH = 4;

parameter ADDRESSWIDTH = 32;

parameter FIFODEPTH = 32; // must be at least twice MAXBURSTCOUNT in order to be efficient

parameter FIFODEPTH_LOG2 = 5;

parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead

...

input user_write_buffer;

input [DATAWIDTH-1:0] user_buffer_data;

wire [FIFODEPTH_LOG2-1:0] fifo_used;

...

output wire [DATAWIDTH-1:0] master_writedata;

...

wire read_fifo;

...

...

...

// write data feed by user logic

scfifo the_user_to_master_fifo (

.aclr (reset),

.usedw (fifo_used),

.clock (clk),

.data (user_buffer_data),

.almost_full (user_buffer_full),

.q (master_writedata),

.rdreq (read_fifo),

.wrreq (user_write_buffer)

);

defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;

defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;

defparam the_user_to_master_fifo.lpm_showahead = "ON";

defparam the_user_to_master_fifo.almost_full_value = (FIFODEPTH - 2);

defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";

defparam the_user_to_master_fifo.add_ram_output_register = "OFF"; // makes timing the burst begin single simplier

defparam the_user_to_master_fifo.underflow_checking = "OFF";

defparam the_user_to_master_fifo.overflow_checking = "OFF";

endmodule

The whole program is from burst_write_master.v in

http://www.altera.com/support/examples/download/exm_avalon_mm_master_templates.zip

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Of course FIFO usedw "has" more than one bit. I guess, you didn't tell the real problem. If you are actually trying to access usedw in Signaltap II or Quartus simulator, you apparently searched the node in the wrong place. It has to be accessed at it's source, in the FIFO compenent directly.

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