use verlog ip in vhdl

I'm trying to use a verilog ip in a vhdl file, first component declaration , then instantiation ... But I keep getting : design library work does not contain ... although I added the file to my project ?

architecture arch of touchtop_01 is
...
component i2c_touch_config is
   port (
      iCLK : out std_logic ;
      iRSTN : out std_logic ;
      iTRIG : out std_logic ;
      oREADY : in std_logic;
      oREG_X1 : in std_logic_vector(9 downto 0);
      oREG_Y1 : in std_logic_vector(8 downto 0);
      oREG_X2 : in std_logic_vector(9 downto 0);
      oREG_Y2 : in std_logic_vector(8 downto 0);
      oREG_TOUCH_COUNT : in std_logic_vector(1 downto 0);
      oREG_GESTURE : in std_logic_vector(7 downto 0);
      I2C_SCLK : in std_logic;
      I2C_SDAT : inout std_logic 
      
      
   );
end component ;
    
    begin
    
     terasictouch :  entity work.i2c_touch_config
                   port map (
                   iCLK => iCLK ,
                iRSTN => iRSTN,
                iTRIG => iTRIG,
                oREADY => oREADY,
                oREG_X1 => oREG_X1,
                oREG_Y1 => oREG_Y1,
                oREG_X2 => oREG_X2,
                oREG_Y2 => oREG_Y2,
                oREG_TOUCH_COUNT => oREG_TOUCH_COUNT,
                oREG_GESTURE => oREG_GESTURE,
                I2C_SCLK => I2C_SCLK,
                I2C_SDAT => I2C_SDAT
                   
                   ) ;
...